[1] Ajay Rupani and Gajendra Sujediya. A review of fpga implementation of internet of things. International Journal of Innovative Research in Computer and Communication Engineering, 4(9), 2016.
[2] Greg Stitt, Robert Karam, Kai Yang, and Swarup Bhunia. A uniquified virtualization approach to hardware security. IEEE Embedded Systems Letters, 9(3):53–56, 2017.
[3] Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri, and Gowtham Kumar Naik. Hardware trojan insertion by direct modification of fpga configuration bitstream. IEEE Design & Test, 30(2):45–54, 2013.
[4] Stephen M Trimberger and Jason J Moore. Fpga security: Motivations, features, and applications. Proceedings of the IEEE, 102(8):1248– 1265, 2014.
[5] Jie Li and John Lach. At-speed delay characterization for ic authentication and trojan horse detection. In 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, pages 8–14. IEEE, 2008.
[6] Sharareh Zamanzadeh and Ali Jahanian. Asic design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow. ISeCure, 8(2), 2016.
[7] Maxime Lecomte, Jacques Fournier, and Philippe Maurine. An on-chip technique to detect hardware trojans and assist counterfeit identification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(12):3317–3330, 2016.
[8] Mainak Banga and Michael S Hsiao. A novel sustained vector technique for the detection of hardware trojans. In 2009 22nd international conference on VLSI design, pages 327–332. IEEE, 2009.
[9] Jiaji He, Yiqiang Zhao, Xiaolong Guo, and Yier Jin. Hardware trojan detection through chip-free electromagnetic side-channel statistical analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(10):2939–2948, 2017.
[10] Mansoureh Labbafniya and Roghaye Saeidi. Secure fpga design by filling unused spaces. ISeCure-The ISC International Journal of Information Security, 11(1):47–56, 2019.
[11] Mansoureh Labafniya, Stjepan Picek, Shahram Etemadi Borujeni, and Nele Mentens. On the feasibility of using evolvable hardware for hardware trojan detection and prevention. Applied Soft Computing, page 106247, 2020.
[12] Kris Tiri and Ingrid Verbauwhede. A logic level design methodology for a secure dpa resistant asic or fpga implementation. In Proceedings Design, Automation and Test in Europe Conference and Exhibition, volume 1, pages 246–251. IEEE, 2004.
[13] Sharareh Zamanzadeh and Ali Jahanian. Security path: An emerging design methodology to protect the fpga ips against passive/active design tampering. Journal of Electronic Testing, 32(3):329–343, 2016.
[14] Franck Courbon, Philippe Loubet-Moundi, Jacques JA Fournier, and Assia Tria. A high efficiency hardware trojan detection technique based on fast sem imaging. In 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 788–793. IEEE, 2015.
[15] Sanchita Mal-Sarkar, Robert Karam, Seetharam Narasimhan, Anandaroop Ghosh, Aswin Krishna, and Swarup Bhunia. Design and validation for fpga trust under hardware trojan attacks. IEEE Transactions on Multi-Scale Computing Systems, 2(3):186–198, 2016.
[16] Ahmad Shabani and Bijan Alizadeh. Pmtp: A max-sat based approach to detect hardware trojan using propagation of maximum transition probability. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 2018.
[17] Marie-Lise Flottes, Sophie Dupuis, Papa-Sidy Ba, and Bruno Rouzeyre. On the limitations of logic testing for detecting hardware trojans horses. In 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pages 1–5. IEEE, 2015. [18] Uthman Alsaiari and Fayez Gebali. Hardware trojan detection using reconfigurable assertion checkers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(7):1575– 1586, 2019.
[19] Paris Kitsos and Artemios G Voyiatzis. Fpga trojan detection using length-optimized ring oscillators. In 2014 17th Euromicro Conference on Digital System Design, pages 675–678. IEEE, 2014.
[20] Kan Xiao and Mohammed Tehranipoor. Bisa: Built-in self-authentication for preventing hardware trojan insertion. In 2013 IEEE international symposium on hardware-oriented security and trust (HOST), pages 45–50. IEEE, 2013.
[21] Papa-Sidy Ba, Manikandan Palanichamy, Sophie Dupuis, Marie-Lise Flottes, Giorgio Di Natale, and Bruno Rouzeyre. Hardware trojan prevention using layout-level design approach. In 2015 European Conference on Circuit Theory and Design (ECCTD), pages 1–4. IEEE, 2015.
[22] Behnam Khaleghi, Ali Ahari, Hossein Asadi, and Siavash Bayat-Sarmadi. Fpga-based protection scheme against hardware trojan horse insertion using dummy logic. IEEE Embedded Systems Letters, 7(2):46–50, 2015.
[23] Hoyoung Yu, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. Recent advances in fpga reverse engineering. Electronics, 7(10):246, 2018.
[24] Jean-Baptiste Note and Éric Rannaud. From the bitstream to the netlist. In FPGA, volume 8, pages 264–264, 2008.
[25] Mohammad Saleh Samimi, Ehsan Aerabi, Zahra Kazemi, Mahdi Fazeli, and Ahmad Patooghy. Hardware enlightening: No where to hide your hardware trojans! In 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS), pages 251–256. IEEE, 2016.
[26] Sophie Dupuis, Papa-Sidi Ba, Giorgio Di Natale, Marie-Lise Flottes, and Bruno Rouzeyre. A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In 2014 IEEE 20th International OnLine Testing Symposium (IOLTS), pages 49–54. IEEE, 2014.
[27] Andrea Marcelli, Marco Restifo, Ernesto Sanchez, and Giovanni Squillero. An evolutionary approach to hardware encryption and trojan-horse mitigation. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, pages 1593–1598. IEEE, 2017.
[28] Srinath Perera. Hadoop MapReduce Cookbook. Packt Publishing Ltd, 2013.
[29] Christoph Albrecht. Iwls 2005 benchmarks. In International Workshop for Logic Synthesis (IWLS): http://www. iwls. org, 2005.
[30] Li Shang, Alireza S Kaviani, and Kusuma Bathala. Dynamic power consumption in virtexâĎć-ii fpga family. In Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, pages 157–164, 2002.